1. Technical Field
The disclosure relates in general to a display device and a driving method applicable thereto, and more particularly to a display device and a driving method applicable thereto in which the display driving circuit not receiving effective display data is temporarily turned off, and before receiving data, the display driving circuits resume the normal mode for preparing the synchronous timing signal to receive display data.
2. Background
A flat display may include multiple display driving circuits (such as source driving circuits). In the flat display with multiple display driving circuits, most of the display driving circuits receive a system clock signal and generate and maintain a synchronous timing signal during most of the operating time, so that the display driving circuits can maintain timing synchronicity to avoid data miss or wrong data fetch. However, during most of the operating time, most of the display driving circuits do not really receive the display data. Here, the display driving circuits receive the display data for driving a display panel (not illustrated) of the display device. Since the system still has to provide power to the display driving circuits not receiving the display data, the power consumption of the system cannot be reduced.
Referring to FIG. 1, a prior driving timing diagram of display driving circuits is shown. Suppose the display having five display driving circuits 110_1˜110_5. The actual operating period T of each display driving circuit must be long enough until all display data have been received by the display driving circuit. The designations T1˜T5 respectively denote the actual operating periods of the five display driving circuits 110_1˜110_5. The signal X denotes a signal which controls the display driving circuit to receive data, and Y denotes a start pulse. The signal Y is delivered to the first display driving circuit 110_1 by a timing controller (not illustrated) to inform when to start to receive the display data. A previous display driving circuit generates the signal X and delivers to the rear display driving circuit. The signal Y is delivered to all display driving circuits when the frame starts.
Within the period T1, the display driving circuit 110_1 receives a display data, and the display driving circuits 110_2˜110_5 despite not receiving the display data still have to generate a synchronous timing signal. Likewise, within the period T2, the display driving circuit 110_1 may be turned off (because it already receives the required display data), the display driving circuit 110_2 starts to receive a display data, and the display driving circuits 110_3˜110_5 despite not receiving the display data still have to generate the synchronous timing signal. Thus, the display driving circuits at the rear (that is, the display driving circuit(s) farther away form the timing controller, such as the display driving circuit 110_5) waste more power on maintaining the synchronous timing signal.
Within a frame period, each display driving circuit receives the display data for a short period of time but receives the system clock signal for the entire frame period, and this is another factor causing extra power consumption.